Switching capacitive DC-DC voltage converters typically use “flying capacitors”. These capacitors are charged from the input voltage and then discharged to the load thus providing charge transfer and a constant output voltage.
FIG. 1 shows a basic known DC-DC converter circuit.
The circuit comprises a switching capacitor Csw. One terminal is connected to the input through a first switch S1 and to the output through a third switch S3. The other terminal is connected to the input through a fourth switch S4 and to ground through a second switch S2.
Basic DC-DC converters of this type integrate switches S1 to S4 and an oscillator so that the switches work alternately in pairs S1,S2 and S3,S4.
The oscillator is shown as a clock signal Clk, and it is passed to the switches in dependence on whether the output voltage Vout has reached a target voltage Vref. An AND gate 10 controls the passing of the clock signal, and a comparator compares the output voltage (or a voltage derived from the output voltage) with the reference level Vref. The comparator output is used to control whether the AND gate passes the clock signal. The comparator output is thus a control signal PUMP which controls the converter pumping. When it is high, the cyclic charge pumping is enabled, and when it is low, the cycles are halted.
The configuration shown doubles the input voltage.
The DC-DC converter operates in two phases, sequenced by the clock. Closing switches S1 and S2 charges the switching capacitor Csw to the input voltage Vin in a first half cycle (storing phase). In the second half cycle, switches S3 and S4 close and switches S1 and S2 open (loading phase). This action connects the negative terminal of Csw to Vin and connects the positive terminal to Vout. If the voltage across the output load Cload is smaller than that across Csw, charge flows from Csw to Cload.
The storing phase and loading phase occur alternately, boosting the DC-DC converter output voltage until its target value Vref is reached. When Vout reaches Vref, the switching clock is stopped, and then the DC-DC converter stays in the storing phase.
As soon Vout goes below Vref, the DC-DC converter restarts pumping, alternating the storing and loading phases until Vout again rises above Vref.
The DC-DC converter output voltage should be regulated within a voltage window by using a voltage hysteresis of the comparator 12. In this way, Vout is regulated between Vref and Vref+Hyst. The threshold voltage for the Vout rising edge is Vref+Hyst, and the threshold voltage for the falling edge is Vref.
FIG. 2 shows this operation, and shows the voltage waveform of the output voltage Vout, which fluctuates between Vref and Vref+Hyst.
During a start-up time, the DC-DC converter pumps energy from Vin to Vout, and Vout rises to Vref+Hyst. The DC-DC converter then stops by staying in a storing state. This is shown as phase P1, and it corresponds the signal PUMP being low, waiting for the output voltage to drop back to Vref.
During phase P1, Vout falls linearly due to the output load current until Vref, and then the DC-DC converter restarts to boost Vout until Vref+Hyst. This boosting involves alternate loading phases P2 and storing phase P3.
For the basic DC-DC converter topology, assuming a fast DC-DC output rising edge, the DC-DC output switching noise varies with respect to the DC-DC converter output regulation window and the DC-DC load current:
                              FSW          DCDC                =                  ILOAD                      CLOAD            ×            Δ            ⁢                                                  ⁢            V                                              [        1        ]            With:                FSWDCDC is the DC-DC switching frequency        ILOAD is DC-DC converter load current        ΔV is the output regulation window        CLOAD is the output capacitance of the DC-DC converter.        
DC-DC converters of this type have application in many different fields. One example is for near field communication (“NFC”) applications, such as RFID applications. NFC systems are for example used for contactless secure communication with a smart card. In this application, an NFC device can operate in card mode or in reader mode.
In card mode, the NFC device acts as a contactless smart card, whereas in reader mode, the NFC device acts as a contactless smart card reader.
When operating in reader mode, the NFC product sends a magnetic field for powering the card (the voltage from the field energy is filtered by the card to generate a supply voltage for the card) and for data exchange between the card and the NFC device. This communication makes use of amplitude modulation.
The NFC front end executes RF polling loops for detecting the card. Once a card is introduced inside the field, data exchanges are performed.
Generally, the card is inserted into the NFC field from top to bottom, as shown in FIG. 3, which shows the reader 30 and card 32. The reader is supplied by a front end 34 through an EMC (electromagnetic compatibility) and matching filter 36.
The main market for this type of contactless NFC device is mobile application. In such customer applications, the NFC circuitry is supplied directly from the mobile battery. These NFC devices should operate over the battery voltage range.
To provide a constant communication distance, the supply voltage of the NFC transmitter should be stable over the battery voltage range. For providing a higher communication distance, the supply voltage of the NFC transmitter should be as high as possible. To meet high and stable communication distance, a DC-DC boost converter is needed for supplying the NFC transmitter from the mobile device battery.
The DC-DC converter for example is embedded on silicon. The stable communication distance can be met using existing circuits, but the operation of the DC-DC converter can induce instability on the NFC communication. When operating, the DC-DC converter generates noise which can disturb the NFC communication. RF degradation can appear if the fundamental component of the DC-DC converter noise is within the RF bandwidth. For NFC applications, the communication bandwidth typically ranges from 100 KHz to 1 MHz.
Thus, the issue of switching noise in the DC-DC converter is of particular concern when the converter is used within an RF circuit such as an NFC device.
FIG. 4 shows as plot 40 a measure of the DC-DC noise frequency based on the distance between the NFC reader antenna and the card (using the right hand y-axis scale). Plot 42 shows the NFC transmitter current consumption (using the left hand y-axis scale).
The left y-axis plots the transmitter current consumption in mA and the right y-axis plots the DC-DC switching frequency in kHz. The x-axis plots the communication distance in mm.
The range 44 represents the NFC bandwidth from 100 kHz to 1 MHz and as shown it includes the DC-DC converter switching noise frequency.
The current consumption of the NFC transmitter increases when the card is closer to the antenna. As it is the load for the DC-DC converter, the DC-DC switching frequency increases. In this example, above 1.5 mm distance, the DC-DC converter switching noise is within the NFC bandwidth and thus able to degrade the RF performance. There is thus a problem that the switching frequency of a basic capacitive DC-DC converter varies with the load current. The DC-DC converter noise frequency is not predictable if the load current is not fixed.